A clock and data recovery unit
1. Technical Field
The invention refers to a clock and data recovery unit and a method for clock and data recovery which are provided for recovery of data pulses which have been subjected to severe noise on a transmission line/channel.
2. Background Art
The band limitation of the transmission channel results in the data signal at the receiver being subjected to distortion caused by intersymbol interference (ISI). The received signal itself contains both deterministic and stochastic edge noise.
The clock and data recovery unit according to the present invention provides for a reliable recovery of the data in a severely noisy environment and can be used in a multichannel application (Multiple Lane Application). The achieved BER is very low (Error rate BER<10^−15) even when the received data signal has only a small eye opening.
For high-speed data transmission, the requirements for the transceiver modules to have high speeds, low bit error rates (Bit Error Rate BER) and a long range are becoming more stringent. Depending on the channel and transmission medium, it is necessary to transmit data in the Gigahertz range, for example at 2.488 Gbit/s to 10 Gbit/s, with as few bit errors as possible.
The circuits for data recovery within the transceiver modules are referred to as clock and data recovery units (CDR). There are two fundamental concepts for data recovery according to the state of the art, i.e. phase alignment and phase picking.
FIG. 1 shows a clock and data recovery unit according to the state of the art as employed in a digital receiver.
Caused by clock jitter, band limitation of the data channels, intersymbol interferences (ISI) as well as reflections and crosstalk between the channels the effective usable signal eye opening is only approximately 35% or even smaller than of the respective data bit cell, so that in a 3,125 Gbit/s real bit data stream (NRZ=non return to zero)-modulated data has only a signal eye opening for each unit interval (UI) having a length of 112 ps while the rest of the bit cell is disturbed by clock jitter, intersymbol interferences (ISI) and reflections.
In the phase adjustment (phase alignment) method according to the state of the art a phase locked loop (PLL) is used to set the sampling time to the signal eye center of the received signal (bit cell). An edge-control D-flipflop which is generally used for recovering and synchronization samples the data applied at the D-input by means of the rising edge at the clock input.
FIG. 2 shows a PLL-based clock recovery system according to the state of the art.
In the phase picking method according to the state of the art in simple terms, the input signal is oversampled by connecting two or more D-flipflops in parallel, which are clocked with stepped clock phases. For data recovery, a control circuit then chooses the output of that D-flip-flop whose clock phase represents the optimum sampling time in the eye center.
Both conventional methods can be implemented in widely differing ways. Different kinds of both multiphase circuits or phase locked loops PLL can be used for implementation of the phase alignment method and the phase picking method.
Both conventional methods according to the state of the art require a phase detector PD, which assesses the phase angle φ of the input data signal with respect to the clock phase φCLK within the clock and data recovery unit. A digital phase detector PD can be regarded as an edge-control switching mechanism to which the received signal on the one hand and a clock phase on the other hand are supplied, and which detects the phase angle φ by means of international stage transitions. One fundamental disadvantage of such digital phase detectors PD is the fact that the received signal is normally distorted and interfered with by various unavoidable effects in the transmission channel, such as reflections, attenuation, channel crosstalk and intersymbol interference (ISI).
In conventional phase adjustment methods according to the state of the art a digital phase detector PD is provided in which the received data signal acts directly on edge-sensitive inputs, so that the above mentioned signal disturbances generally lead to incorrect assessments of the phase angle φ. Provided that they do not occur excessively frequently, these incorrect assessments can be sufficiently suppressed by use of a very inert control system so that the signal disturbances do not immediately lead to unlocking of the phase locked loop PLL. However, an incorrect assessment of the phase angle φ leads to a reduction in the jitter budget even when using an inert control system, so that the received data signal needs to have a larger signal eye opening for the same bit error rate BER than would be the case with a phase detector PD that is less sensitive to the above mentioned signal disturbances. A further disadvantage of a inert control system is that the phase locked loop PLL takes longer to lock in.
With the conventional phase alignment methods, the data detection (recovery) is carried out at the data rate DR. The control loop for phase adjustment does not have to achieve the BER<10^−15, but the regenerative flipflop must have appropriate stability. Metastability of the flipflop leads to incorrect decisions in data recovery.
In order to avoid these disadvantages of phase adjustment methods in phase picking CDRs according to the state of the art the phase information is not obtained directly from the received data input signal, but the received data signal is oversampled and the phase angle φ is derived from the oversampled signal.
FIG. 3a, 3b show a phase picking data recovery system according to the state of the art.
In a phase picking data recovery system as shown in FIG. 3a multiple clock phases sample each data bit from the received serial data stream at multiple positions. The phase picking data recovery system detects data transitions and picks the data sample which is furthest away from the detected data transition. By delaying the data samples while the decision is made the phase picking data recovery system as shown in FIG. 3a employs a feed forward loop. Because stability constrains are absent the phase picking method achieves a very high bandwidth and track phase movements on a cycle-cycle-basis. However, the tracking can occur only at quantisised steps depending on the degree of oversampling. The phase picking decision causes some latency.
A principle disadvantage of conventional phase alignment methods and phase picking methods according to the state of the art is that only a small part of the received data signal is effectively used for the decision, wherein the usable signal part is defined by the position of the clock edge and the set and hold times of the decision circuit. To avoid infringement of the setup and hold times of the decision circuit which causes a metastability and so to a undefined logic value the decision circuit is implemented such that its setup and hold times are as small as possible. Accordingly the signal part around the clock edge which is in fact evaluated is very short and accordingly the evaluated signal energy is very low. High frequent disturbances such as high frequent noise leads in particular at very small signal eyes to an increased bit error rate (BER). Undesired high frequent noise can be provided on the supply voltage of the clock and data recovery unit or can be applied together with the received data signal.
To avoid the sensitivity of the clock and data recovery unit because of the small signal power of the sampled signal it is known to use current integrating receivers. In this current integrating receivers the differential data input signal is integrated during a time period corresponding to the unit interval UI of a bit cell. At the end of the bit cell it is evaluated whether the current integral is positive or negative to recover the data bit. However, in a communication system wherein the usable signal eye opening is only in the range of 35% or even smaller of the received bit cell a current integrating receiver can not be employed, because the distorted and disturbed signal portions would be outside the usable signal eye opening.
FIG. 4 shows a conventional binary phase detection (BPD) circuit as employed in a clock and data recovery unit according to the state of the art, wherein a phase picking method is used. The received digital data signal is oversampled by an oversampling unit which generates data samples Si. EXOR gates compare neighboring data samples Si to decide whether a data transition has occurred. The EXOR gates are connected on the output side to summation means to calculate the phase difference Δφ between the incoming serial data bit stream and a reference time. The output signal of the binary phase detector BPD is supplied to a loop filter. The loop filter is a low path filter (LPF) having the following open loop transfer function:
                                          ϕ            out                                ϕ                          i              ⁢                                                          ⁢              n                                      =                                            A              0                        ⁡                          (              DD              )                                            1            +                          s                              w                P                                      +                                          A                0                            ⁡                              (                DD                )                                                                        (        1        )            wherein DD is the data density of received serial data bit stream.
FIG. 5 shows the loop gain of the data and recovery unit according to the state of the art as shown in FIG. 4 for a conventional low path loop filter (LPF).
As can be seen from FIG. 5 the loop gain is decreased when the data density DD of the received serial date bit stream is lowered.
FIG. 6a shows the phase detector gain PDG of the conventional clock and data recovery unit having a binary phase detector BPD as shown in FIG. 4. As can be seen from FIG. 6a the lower the data density DD of the received serial data bit stream is, i.e. the lower the number of detected data transitions is the smaller is the phase detector gain PDG. The lower the data density DD of the received serial bit stream is, the lower is the number of data transitions which include the information for adjusting the phase of the clock signal to be recovered.